- Timestamp:
- 10/04/09 12:36:56 (15 years ago)
- Files:
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- 1 modified
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vtcross/branches/sriram/rfic/db_rfic.cc
r483 r500 328 328 bool set_tx_gain(float); 329 329 void set_fb_gain(float); 330 int* calc_freq_vars(double,double);331 int* calc_phase_vars(double,double,double);330 void calc_freq_vars(double,double,int []); 331 void calc_phase_vars(double,double,double,int[]); 332 332 struct freq_result_t set_rx_freq(double); 333 333 struct freq_result_t set_tx_freq(double); … … 870 870 rfic::send_reg(int reg_no,int dat ) 871 871 { 872 std::cout<<"value to be written on reg no "<<reg_no<<"is "<<dat<<std::endl;872 873 873 // dat is the data to write to register 0 874 874 //spi_enable is the spi enables … … 878 878 //Write 8 bit register 879 879 //Set header 880 int hdr = int((reg_no << 1) & 0x7fff); 881 std::string abc = "105"; 882 //Set byte of write data 883 //char c = (char)((dat & 0xff)); 884 //char * d = &c; 885 880 881 std::cout<<"db_rfic.cc: Register no: "<<reg_no<<" ,Value: "<<dat<<std::endl; 882 //std::cout<<"db_rfic.cc:Value on the register before writing"<<get_reg(reg_no)<<std::endl; 883 884 int hdr = int((reg_no << 1) & 0x7fff); //since the 14 bit address lies from bits 1-14..0th bit is for auto increment..15th bit is for read/write 885 char c[1]; 886 c[0] = (char)(dat&0xff); 887 std::string s(c, 1); //s is the data to be sent to the register 888 886 889 bool check; 887 std::cout<<"\nValue on the register before writing\n"<<get_reg(reg_no)<<std::endl;888 check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, abc);889 if (check)890 std::cout<<"success"<<std::endl;891 else892 std::cout<<"fail"<<std::endl;893 std::cout<<"\nValue on the register after ******** writing\n ***"<<get_reg(reg_no)<<"***"<<std::endl;894 890 891 check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, s); 892 //if (check) 893 //std::cout<<"db_rfic.cc: Write successful"<<std::endl; //Do not trust variable check! 894 //else 895 //std::cout<<"db_rfic.cc: Write failed"<<std::endl; 896 //std::cout<<"db_rfic.cc:Value on the register after ******** writing\n ***"<<get_reg(reg_no)<<"***"<<std::endl; 897 //if(reg_no == 60) 898 //get_reg(reg_no); 895 899 } 896 900 … … 899 903 { 900 904 901 std::cout<<"inside get reg and register to be read is "<<reg_num<<std::endl; 902 //Returns a vector containing the information in the first 320 registers in integer form 905 //Returns a vector containing the information in the first 320 registers in integer form 903 906 //dat is the data to write to register 0 904 907 //spi_enable is the spi enables … … 906 909 //spi_format_no_header is the spi format, with no header 907 910 //u is the instance of the USRP 911 908 912 int hdr = 0; 909 913 int dat = 0; 910 //Set byte of write data911 //char c = (char)((dat & 0xff));912 //char * d = &c;913 std::string d = "0";914 char c[1]; 915 c[0] = (char)(dat&0xff); 916 std::string s(c, 1); //s is the data to be sent to the register 917 914 918 bool check; 915 check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, d);919 check = usrp()->_write_spi(hdr, d_spi_enable, d_spi_format, s); 916 920 917 921 std::string r; //string to be read from the register 918 r = usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 922 r = usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); //Starts reading from register 0 since the previous write is on register 0 919 923 r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 920 924 r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 921 925 r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 922 926 r = r + usrp()->_read_spi(0, d_spi_enable, d_spi_format_no_header, 64); 923 std::cout<<" the contents of all registers are\n***"<<r<<"*****"<<std::endl;927 std::cout<<"db_rfic.cc: contents of all registers \n***"<<r<<"***"<<std::endl; 924 928 char read_val = (char)r[reg_num]; 925 929 return read_val; … … 2378 2382 } 2379 2383 2380 int* rfic :: calc_freq_vars(double _Fclk,double _Fout){2384 void rfic :: calc_freq_vars(double _Fclk,double _Fout,int ret_arr[]){ 2381 2385 // 2382 2386 //@param Fclk: Clock frequency of board (Hz) … … 2394 2398 float NpR; 2395 2399 int data1,data2,data3,temp,Ngt; 2396 int ret_arr[6];2400 //int ret_arr[6]; 2397 2401 if (_Fout > _Fclk / 4){ 2398 2402 NpR = pow(2,-26) * floor(pow(2,26) * _Fclk / _Fout); … … 2408 2412 } 2409 2413 2410 Ngt = data1;//need to speak to terry about this variable..is this a local variable or supposed to be a class attribute 2414 Ngt = data1; 2415 2411 2416 ret_arr[0]= Ngt; 2412 2417 NorNdiv4 = data2; 2413 2418 ret_arr[1]=NorNdiv4; 2419 2414 2420 RorFrNpRdiv4_25to18 = data3 >> 18; 2415 2421 ret_arr[2]=RorFrNpRdiv4_25to18; … … 2422 2428 RorFrNpRdiv4_1to0 = data3 % int(pow(2,2)); 2423 2429 ret_arr[5]=RorFrNpRdiv4_1to0; 2424 2425 return ret_arr; 2426 } 2427 2428 int* rfic :: calc_phase_vars(double _Fclk, double _Fout,double phsh){ 2430 2431 } 2432 2433 void rfic :: calc_phase_vars(double _Fclk, double _Fout,double phsh,int ret_arr[]){ 2429 2434 // 2430 2435 //@param _Fclk: Clock frequency of board (Hz) … … 2445 2450 float mod1,tmp,NpR,NpR_ph; 2446 2451 int data1,data2,data3,temp,Ngt_phsh,RorFrNpRdiv4_17to10_phsh,RorFrNpRdiv4_9to2_phsh,RorFrNpRdiv4_25to18_phsh,RorFrNpRdiv4_1to0_phsh; 2447 int ret_arr[6];2452 2448 2453 if (_Fout <= _Fclk / 4){ 2449 2454 mod1 = phsh - 360 * floor(phsh / 360); … … 2476 2481 Ngt_phsh = data1; 2477 2482 ret_arr[0]=Ngt_phsh; 2483 2478 2484 NorNdiv4_phsh = data2; 2479 2485 ret_arr[1]=NorNdiv4_phsh; … … 2489 2495 ret_arr[5]=RorFrNpRdiv4_1to0_phsh; 2490 2496 2491 return ret_arr;2492 2497 } 2493 2498 … … 2744 2749 2745 2750 Foutrx = target_freq; 2746 int * ret_arr;2747 ret_arr= calc_freq_vars(Fclk, try_freq);2751 int ret_arr[6]; 2752 calc_freq_vars(Fclk, try_freq,ret_arr); 2748 2753 Ngt3_3 = ret_arr[0]; 2749 NorNdiv4_3= ret_arr[1]; 2750 RorFrNpRdiv4_25to18_3= ret_arr[2]; 2751 RorFrNpRdiv4_17to10_3= ret_arr[3]; 2752 RorFrNpRdiv4_9to2_3= ret_arr[4]; 2753 RorFrNpRdiv4_1to0_3= ret_arr[5]; 2754 NorNdiv4_3= ret_arr[1]; 2755 RorFrNpRdiv4_25to18_3= ret_arr[2]; 2756 RorFrNpRdiv4_17to10_3= ret_arr[3]; 2757 RorFrNpRdiv4_9to2_3= ret_arr[4]; 2758 RorFrNpRdiv4_1to0_3= ret_arr[5]; 2759 2754 2760 2755 2761 set_reg_104(); … … 2971 2977 Fouttx = target_freq; 2972 2978 2973 int * ret_arr;2974 ret_arr= calc_freq_vars(Fclk, try_freq);2979 int ret_arr[6]; 2980 calc_freq_vars(Fclk, try_freq,ret_arr); 2975 2981 Ngt3 = ret_arr[0]; 2976 2982 NorNdiv4= ret_arr[1]; … … 3160 3166 } 3161 3167 Foutfb = target_freq; 3162 int * ret_arr;3163 ret_arr= calc_freq_vars(Fclk, try_freq);3168 int ret_arr[6]; 3169 calc_freq_vars(Fclk, try_freq,ret_arr); 3164 3170 Ngt3_2 = ret_arr[0]; 3165 3171 NorNdiv4_2= ret_arr[1]; … … 3200 3206 synth_freq = Foutrx / 4; 3201 3207 3202 int * ret_arr;3203 ret_arr= calc_phase_vars(Fclk, synth_freq,phsh);3208 int ret_arr[6]; 3209 calc_phase_vars(Fclk, synth_freq,phsh,ret_arr); 3204 3210 Qu_tx_Ngt3_3 = ret_arr[0]; 3205 3211 NorNdiv4_phsh_3= ret_arr[1]; … … 3238 3244 synth_freq = Fouttx / 4; 3239 3245 3240 int * ret_arr;3241 ret_arr= calc_phase_vars(Fclk, synth_freq,phsh);3246 int ret_arr[6]; 3247 calc_phase_vars(Fclk, synth_freq,phsh,ret_arr); 3242 3248 Qu_tx_Ngt3_3 = ret_arr[0]; 3243 3249 NorNdiv4_phsh_3= ret_arr[1]; … … 3276 3282 3277 3283 3278 int * ret_arr;3279 ret_arr= calc_phase_vars(Fclk, synth_freq,phsh);3284 int ret_arr[6]; 3285 calc_phase_vars(Fclk, synth_freq,phsh,ret_arr); 3280 3286 Qu_tx_Ngt3_3 = ret_arr[0]; 3281 3287 NorNdiv4_phsh_3= ret_arr[1];